This application claims benefit of priority under 35 U.S.C. xc2xa7119 to Japanese Patent Application No. 2002-163758, filed on Jun. 5, 2002, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to an output buffer circuit including a driving capability control circuit which performs control to change driving capability of an output buffer during its operation.
2. Description of the Related Art
With a recent remarkable increase in the operation speed of an integrated circuit, a high-speed output buffer has also been demanded of its output buffer. To meet this demand, improvements in the driving capability of the output buffer are made, but the improvements caused the problem of noises such as overshoot, undershoot, and ringing.
Hence, the output buffer has been faced the contradictory demands, that is, an improvement in driving force and a reduction in noise at the same time.
One of solutions thereto is to change the driving capability of the output buffer during its operation. The increase in speed demanded of the output buffer of a digital circuit means that the signal reaches earlier to the logical threshold of the next stage, and therefore high driving capability is required for the output buffer from the start of state transition to its arrival at the logical threshold level of the next stage.
On the other hand, noise tends to occur after the output signal reaches the logical threshold of the next stage, and especially when the driving capability is high, noise markedly occurs. To reduce the noise, it is effective to reduce the driving capability of the output buffer after the signal reaches the logical threshold of the next stage.
FIG. 6 shows the circuit configuration of a related complementary MIS output buffer control circuit. An input 101 is connected to a main buffer 103 of an output buffer via a subbuffer 102. The main buffer 103 is connected to an output terminal 104 and drives a load capacitance 105. A driving assistant buffer 106 including a P-channel MISFET (hereinafter referred to as a P-MIS) 1061 for enhancing rise driving force and an N-channel MISFET (hereinafter referred to as an N-MIS) 1062 for enhancing fall driving force is connected in parallel with the main buffer 103.
A two-input NAND 108 is connected to a gate terminal of the P-MIS 1061, and a two-input NOR 109 is connected to a gate terminal of the N-MIS 1062. Both inputs of the NAND 108 and the NOR 109 are the input 101 and an inverted output by an inverter 107 of the output terminal 104. Namely, on/off control of the driving assistant buffer 106 is performed by the input 101 and a feedback from the output terminal 104.
Incidentally, a parasitic inductance 110 such as a pin, a bonding wire, or the like of an integrated circuit package exists between the output terminal 104 and the load capacitance 105.
Now, the operation of the driving assistant buffer 106 during an output transition is explained. First, when the input 101 is xe2x80x9cHxe2x80x9d and both its input and output are stable, the output terminal 104 is also xe2x80x9cHxe2x80x9d, and hence an output of the inverter 107 is xe2x80x9cLxe2x80x9d. Accordingly, an output of the NAND 108 is xe2x80x9cHxe2x80x9d, and an output of the NOR 109 is xe2x80x9cLxe2x80x9d, whereby both the P-MIS 1061 and the N-MIS 1062 are turned off, that is, the driving assistant buffer 106 does not function.
When the input 101 changes from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d, the output terminal 104 also starts to change from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d, but there exists an output delay time which depends on the magnitude of the load capacitance 105. Accordingly, the output of the inverter 107 remains xe2x80x9cHxe2x80x9d immediately after the change of the input 101 from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d. Therefore, both inputs of the NOR 109 are xe2x80x9cLxe2x80x9d and the output thereof is xe2x80x9cHxe2x80x9d, so that the N-MIS 1062 is turned on.
On the other hand, since the input 101 becomes xe2x80x9cLxe2x80x9d, the output of the NAND 108 remains xe2x80x9cHxe2x80x9d, and the P-MIS 1061 remains off.
Namely, during this period, the driving assistant buffer 106 enhances the driving force which makes an output of the main buffer 103 to fall by turning only the N-MIS 1062 on.
Thereafter, when the level of the output terminal 104 exceeds a logical threshold of the inverter 107, the output of the inverter 107 becomes xe2x80x9cHxe2x80x9d, and the output of the NOR 109 becomes xe2x80x9cLxe2x80x9d, whereby the N-MIS 1062 is turned off. Thus, the operation of the driving assistant buffer 106 is completed. In other words, the driving assistant buffer 106 functions from when the level of the output terminal 104 started to change until it exceeds the logical threshold of the inverter 107.
FIG. 7 is a operation waveform diagram of the output buffer circuit. At early stages of the fall of an output waveform, the output waveform sharply falls since both the main buffer 103 and the driving assistant buffer 106 operate, but when the output level exceeds the logical threshold of the inverter 107, the driving assistant buffer 106 stops its operation, and hence the output change becomes gradual.
Incidentally, when the input 101 changes from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d, the output of the NAND 108 stays xe2x80x9cLxe2x80x9d until the level of the output terminal 104 exceeds the logical threshold of the inverter 107, and the P-MIS 1061 is turned on to thereby increase the speed of output change immediately after rise (not shown in FIG. 7).
Thus, in the circuit in FIG. 6, both the inverter 107 and the NOR 109 or the NAND 108 perform the operation of controlling the driving force of the output buffer in such a manner that the driving force is increased immediately after the output transition and reduced from the middle of the transition.
The related complementary MIS output buffer control circuit, however, has a problem that internal oscillation tends to occur when the driving force is reduced in the middle of the transition. This is because the rate of current change per unit time increases due to a sharp change in driving force and counter electromotive force generated by the product of the current change rate and the parasitic inductance 110 increases to thereby return the output change in the opposite direction.
The output considered as temporarily exceeding the logical threshold of the inverter 107 by this counter electromotive force is considered again as having the logical threshold or less, and the driving assistant buffer 106 is turned on again. Then, the counter electromotive force which acts in the opposite direction to the previous direction is generated, and this time it acts so as to turn off the driving assistant buffer 106. The repetition of this operation causes oscillation, and FIG. 8 shows an example of its simulation.
A factor which causes the sharp change in driving force is a high gain of the driving force control circuit including the inverter 107 and the NAND 108 or the NOR 109 which controls the driving assistant buffer 106.
FIG. 9 shows a portion including the inverter 107 and the NOR 109 extracted from the driving force control circuit with a case when the output terminal 104 changes from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d as an example, and herein the NOR 109 is represented by a MISFET.
In FIG. 9, immediately after the change of the input 101 from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d, the output terminal 104 still remains xe2x80x9cHxe2x80x9d, and a NOR input 1091 which is an inverted output of the inverter 107 remains xe2x80x9cLxe2x80x9d. Accordingly, a NOR output 1092 is xe2x80x9cHxe2x80x9d.
Thereafter, when the output terminal 104 changes to xe2x80x9cLxe2x80x9d, the NOR input 1091 changes to xe2x80x9cHxe2x80x9d. Then, a P-MIS 1093 changes its state from ON to OFF, and an N-MIS 1094 changes its state from OFF to ON, whereby the NOR output 1092 becomes xe2x80x9cLxe2x80x9d. At this time, changes in the states of the P-MIS 1093 and the N-MIS 1094 simultaneously occur, and hence the change of the NOR output 1092 from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d is sharp.
FIG. 10 shows the voltage transition of the NOR output 1092 with respect to the voltage transition of the output terminal 104. The sharper change of the output relative to the change of the input indicates that the gain of this driving force control circuit is high.
Since the output change of the NOR output 1092 is sharp, the N-MIS 1062 of the driving assistant buffer 106 is suddenly turned off during the voltage of 104 is falling down (from right side of the FIG. 10 to the left), and the driving force to the output terminal 104 is reduced brutally.
Due to the high gain of this driving force control circuit, the slope of the output signal of the control circuit is almost constant irrespective of the slope of the voltage transition of the output terminal 104. FIG. 11 shows output waveforms (output waveform 1, output waveform 2) of the NOR output 1092 with respect to two inputs (input waveform 1, input waveform 2) having different slopes of the output terminal 104, and it is found that the slopes of the output waveform 1 and the output waveform 2 are almost the same.
Concerning oscillation caused by the counter electromotive force of the parasitic inductance 110, the problem is that the slope of the output signal of the control circuit is steep with respect to a waveform having a gentle slope like the input waveform 2 in FIG. 11. In the case of a waveform in which the slope of the voltage change of the output terminal 104 is steep, even if some counter electromotive force occurs, the voltage level of the output terminal 104 changes at a speed exceeding the speed of the occurrence, and hence the effects of the counter electromotive force are counteracted, but in the case of a waveform having a gentle slope, the voltage level of the output terminal 104 does not change to such an extent as to counteract the effects of the counter electromotive force, and hence oscillation occurs.
On the other hand, in the case of the waveform in which the slope of the voltage change of the output terminal 104 is steep, it is desirable that the output slope of the driving force control circuit be also steep in order to turn off the driving assistant buffer 106 early. If not, the driving force remains enhanced even in the situation in which noise has to be concerned.
Incidentally, although the case where the input 101 changes from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d is explained so far as an example, also in a case where the input 101 changes from xe2x80x9cLxe2x80x9d to Hxe2x80x9d, oscillation also occurs in the output terminal 104 due to the high gain of the driving force control circuit including the inverter 107 and the NAND 108 which controls the P-MIS 1061.
Namely, there is a problem that oscillation occurs in the output terminal at the time of switching of the control circuit of the complementary MIS output buffer.
FIG. 12 shows a circuit diagram of a circuit configuration of another related complementary MIS output buffer circuit. The complementary MIS output buffer circuit of FIG. 12 is different from the complementary MIS output buffer circuit of FIG. 6 in that inverters 200 and 202 are provided instead of the inverter 107. That is, an input terminal of the inverter 200 is connected to the output terminal 104, and an output terminal of the inverter 200 is connected to the NOR 109. An input terminal of the inverter 202 is connected to the output terminal 104, and an output terminal of the inverter 202 is connected to the NAND 108.
A logical threshold of the inverter 200 is different from that of the inverter 202. As a result, a switching timing of an on/off-state of the P-MIS 1061 can be different from a switching timing of an on/off-state of the N-MIS 1062. However, there is a problem that oscillation occurs in the output terminal at the time of switching in the same manner as mentioned above.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, an output buffer circuit, comprises:
a buffer which is supplied with an input signal and which outputs an output signal from an output terminal;
a driving assistant buffer which includes a first MISFET provided at one of a first position and a second position, the first position being between the output terminal and a first power supply and the second position being between the output terminal and a second power supply;
a first logic circuit which is connected to the output terminal and which has a first logical threshold, the first logic circuit configured to perform a logic operation based on the first logical threshold using the output signal so as to output a first logic signal;
a second logic circuit which is connected to the output terminal and which has a second logical threshold higher than the first logical threshold, the second logic circuit configured to perform the same logic operation as the first logic circuit based on the second logical threshold using the output signal so as to output a second logic signal; and
a third logic circuit which is connected to a gate of the first MISFET and which outputs a control signal so as to control the first MISFET, the third logic circuit including a second MISFET of a P-channel and a third MISFET of an N-channel which are connected in series between a third power supply and a fourth power supply, the first logic signal being inputted to a gate of the second MISFET and the second logic signal being inputted to a gate of the third MISFET.